| Presentation | 2004/1/15 Research on optimization of the processor structure for DCT Atsushi Sekine, Gensuke Goto, Jube Tada, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | DCT is used for a picture or sound extension technology to realize by the system LSI dealing with video signals. Generally, the dedicated processors are needed to process DCT or any other video/audio signals, such as a DSP. However, if a DSP is adopted as a processing element, hardware cost will increase very much. Then, suppressing the increase in hardware cost is necessary as much as possible, and moreover optimizing the structure of a processor is required for high-speed processing. In this research, performance of multiple-accumulate operation and Σ-operation were raised by implementing a major part of DCT as hardware. Speed and hardware cost is compared with respected to conventional multiple-accumulate hardware and Σ-operation machine with a normal processor and a processor-added DCT block. It was shown that the operation speed is 40% faster than normal processor. The cost is 48% lower for the multiple-accumulate hardware and 46% lower for the Σ-operation than processor added the DCT block. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DCT / processor / operation time / multiple-accumulate operation |
| Paper # | VLD2003-116,CPSY2003-25 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 2004/1/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Research on optimization of the processor structure for DCT |
| Sub Title (in English) | |
| Keyword(1) | DCT |
| Keyword(2) | processor |
| Keyword(3) | operation time |
| Keyword(4) | multiple-accumulate operation |
| 1st Author's Name | Atsushi Sekine |
| 1st Author's Affiliation | Yamagata University faculty of technology() |
| 2nd Author's Name | Gensuke Goto |
| 2nd Author's Affiliation | Yamagata University faculty of technology |
| 3rd Author's Name | Jube Tada |
| 3rd Author's Affiliation | Yamagata University faculty of technology |
| Date | 2004/1/15 |
| Paper # | VLD2003-116,CPSY2003-25 |
| Volume (vol) | vol.103 |
| Number (no) | 578 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |