| Presentation | 2004/1/15 Performance Evaluation of a Resource-Shared VLIW Processor Array Masao ARAMOTO, Yoichi YUYAMA, Akihiko HIGUCHI, Junka OKAZAWA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a Resource-Shared VLIW Processor Array which is a VLIW processor on the SMT technology. In the proposed processor array, a compiler (software) statically analyzes the dependency of a variable , and a hardware dynamically assigns execution resources. Therefore, hardware can be utilized as much as possible while its structure becomes very simple. Experimental results show that hardware resources of the proposed processor are used 2.6 times more frequent than a conventional VLIW processor when four parallel resources are prepared. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | VLIW / SMT / resource utilization |
| Paper # | VLD2003-115,CPSY2603-24 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2004/1/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Evaluation of a Resource-Shared VLIW Processor Array |
| Sub Title (in English) | |
| Keyword(1) | VLIW |
| Keyword(2) | SMT |
| Keyword(3) | resource utilization |
| 1st Author's Name | Masao ARAMOTO |
| 1st Author's Affiliation | Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | Yoichi YUYAMA |
| 2nd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 3rd Author's Name | Akihiko HIGUCHI |
| 3rd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 4th Author's Name | Junka OKAZAWA |
| 4th Author's Affiliation | IBM Japan |
| 5th Author's Name | Kazutoshi KOBAYASHI |
| 5th Author's Affiliation | VLSI Design and Education Center, The University of Tokyo |
| 6th Author's Name | Hidetoshi ONODERA |
| 6th Author's Affiliation | Graduate School of Informatics, Kyoto University |
| Date | 2004/1/15 |
| Paper # | VLD2003-115,CPSY2603-24 |
| Volume (vol) | vol.103 |
| Number (no) | 578 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |