Presentation | 2003/5/8 C言語でのハードウェア記述に対する効率的な等価性検証手法の提案(システム設計及び一般) Takeshi MATSUMOTO, Hiroshi SAITO, Masahiro FUJITA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we propose a verification method to check the equivalence of two given C-based hardware descriptions efficiently. The main idea of the method is to extract away the descriptions as much as possible. For this purpose, textual differences between the descriptions are identified at first. Based on these differences, we extract the codes relevant to these differences by using a program slicer. These extracted codes are then verified by using symbolic simulation. Our proposed method was tested on several examples. Since the size of the descriptions was significantly reduced, our proposed method can verify large descriptions. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Equivalence Checking / C-based Design / Program Slicing / Symbolic Simulation |
Paper # | VLD2003-6 |
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Committee | VLD |
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Conference Date | 2003/5/8(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | |
Sub Title (in English) | |
Keyword(1) | Equivalence Checking |
Keyword(2) | C-based Design |
Keyword(3) | Program Slicing |
Keyword(4) | Symbolic Simulation |
1st Author's Name | Takeshi MATSUMOTO |
1st Author's Affiliation | Department of Electronic Engineering, University of Tokyo() |
2nd Author's Name | Hiroshi SAITO |
2nd Author's Affiliation | Research Center for Advanced Science and Technology, University of Tokyo |
3rd Author's Name | Masahiro FUJITA |
3rd Author's Affiliation | Department of Electronic Engineering, University of Tokyo |
Date | 2003/5/8 |
Paper # | VLD2003-6 |
Volume (vol) | vol.103 |
Number (no) | 40 |
Page | pp.pp.- |
#Pages | 6 |
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