| Presentation | 2003/9/22 Compact Modeling of a Flash Memory Cell Including Substrate-Bias-Dependent Hot-Electron Gate Current Ken'ichiro SONODA, Motoaki TANIZAWA, Satoshi SHIMIZU, Yasuhiro ARAKI, Shinji KAWAI, Taku OGURA, Shin'ichi KOBAYASHI, Kiyoshi ISHIKAWA, Yasuo INOUE, Norihiko KOTANI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a compact model for a flash memory cell that is suitable for SPICE simulation. The model includes a hot-electron gate current model that considers not only Channel Hot Electron (CHE) injection but also CHannel Initiated Secondary Electron (CHISEL) injection to express properly substrate bias dependence. Simulation results of both programming and erasing characteristics for 130nm-technology flash memory cells indicate that our model is useful in designing and optimizing circuit for flash memories. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | flash memory / gate current / program / erase / CHE / CHISE / FN |
| Paper # | VLD2003-63 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2003/9/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Compact Modeling of a Flash Memory Cell Including Substrate-Bias-Dependent Hot-Electron Gate Current |
| Sub Title (in English) | |
| Keyword(1) | flash memory |
| Keyword(2) | gate current |
| Keyword(3) | program |
| Keyword(4) | erase |
| Keyword(5) | CHE |
| Keyword(6) | CHISE |
| Keyword(7) | FN |
| 1st Author's Name | Ken'ichiro SONODA |
| 1st Author's Affiliation | Renesas Technology Corp.() |
| 2nd Author's Name | Motoaki TANIZAWA |
| 2nd Author's Affiliation | Renesas Technology Corp. |
| 3rd Author's Name | Satoshi SHIMIZU |
| 3rd Author's Affiliation | Renesas Technology Corp. |
| 4th Author's Name | Yasuhiro ARAKI |
| 4th Author's Affiliation | Renesas Technology Corp. |
| 5th Author's Name | Shinji KAWAI |
| 5th Author's Affiliation | Renesas Technology Corp. |
| 6th Author's Name | Taku OGURA |
| 6th Author's Affiliation | Renesas Technology Corp. |
| 7th Author's Name | Shin'ichi KOBAYASHI |
| 7th Author's Affiliation | Renesas Technology Corp. |
| 8th Author's Name | Kiyoshi ISHIKAWA |
| 8th Author's Affiliation | Renesas Technology Corp. |
| 9th Author's Name | Yasuo INOUE |
| 9th Author's Affiliation | Renesas Technology Corp. |
| 10th Author's Name | Norihiko KOTANI |
| 10th Author's Affiliation | Hiroshima Int'l Univ. |
| Date | 2003/9/22 |
| Paper # | VLD2003-63 |
| Volume (vol) | vol.103 |
| Number (no) | 337 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |