Presentation | 2003/9/22 Problems and Solution of DSM Variability Design in 90nm Era Hiroo Masuda, Masaharu Yamamoto, Shinichi Okawa, Masakazu Aoki, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | For 130nm LSI and Process and beyond, intar-chip variation is one of the crusial issues. Especially Clock-Skew is largely affected by the intar-chip variation. In Low-Power LSI's, reduced supply voltage results in critical design margin problems as well as leakage ones. In 90nm process, it is well recognized that reliability, variability on wafer and yield of LSI's are design matter as well as Process one, which is called DFM(Design for manufacturability). We propose a novel Test-Structure (TEG) which bridges the gap between Variability design and Fab. Process control issues. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Variability / TEG / DFM |
Paper # | VLD2003-59 |
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Committee | VLD |
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Conference Date | 2003/9/22(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Problems and Solution of DSM Variability Design in 90nm Era |
Sub Title (in English) | |
Keyword(1) | Variability |
Keyword(2) | TEG |
Keyword(3) | DFM |
1st Author's Name | Hiroo Masuda |
1st Author's Affiliation | STARC (Semiconductor Technology Academic Research Center)() |
2nd Author's Name | Masaharu Yamamoto |
2nd Author's Affiliation | STARC (Semiconductor Technology Academic Research Center) |
3rd Author's Name | Shinichi Okawa |
3rd Author's Affiliation | STARC (Semiconductor Technology Academic Research Center) |
4th Author's Name | Masakazu Aoki |
4th Author's Affiliation | STARC (Semiconductor Technology Academic Research Center) |
Date | 2003/9/22 |
Paper # | VLD2003-59 |
Volume (vol) | vol.103 |
Number (no) | 337 |
Page | pp.pp.- |
#Pages | 6 |
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