| Presentation | 2003/2/28 Dynamically Reconfigurable MPEG Processor with Block Architecture Kiyotaka KOMOKU, Takayuki MORISHITA, Takashi OHZONE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, the structure of dynamically reconfigurable MPEG processor we developed and the result of design of the functional blocks as reconfigurable unit are shown. The block architecture is proposed as reconfigurable structure for pipeline processing. The functional blocks are designed on Xilinx FPGA XCV-2000E. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable / MPEG / MPEG processor / block architecture / pipeline processing |
| Paper # | VLD2002-160,ICD2002-225 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2003/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dynamically Reconfigurable MPEG Processor with Block Architecture |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable |
| Keyword(2) | MPEG |
| Keyword(3) | MPEG processor |
| Keyword(4) | block architecture |
| Keyword(5) | pipeline processing |
| 1st Author's Name | Kiyotaka KOMOKU |
| 1st Author's Affiliation | Faculty of Computer Science and System Engineering, Okayama Prefectural University() |
| 2nd Author's Name | Takayuki MORISHITA |
| 2nd Author's Affiliation | Faculty of Computer Science and System Engineering, Okayama Prefectural University |
| 3rd Author's Name | Takashi OHZONE |
| 3rd Author's Affiliation | Faculty of Computer Science and System Engineering, Okayama Prefectural UniversityIn this report, the structure of dynamically reconfigurable MPEG processor we developed and the result of design of the functional blocks as reconfigurable unit are shown. The block architecture is proposed as reconfigurable structure for pipeline processing. The functional blocks are designed on Xilinx FPGA XCV-2000E. |
| Date | 2003/2/28 |
| Paper # | VLD2002-160,ICD2002-225 |
| Volume (vol) | vol.102 |
| Number (no) | 684 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |