講演名 | 2003/2/27 Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells , |
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PDFダウンロードページ | PDFダウンロードページへ |
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抄録(英) | The problem of designing VLSI systems is becoming very complex. This complexity can be partially simplified by using PLAs, because of its simplicity, regularity, flexibility, programmability, and predictability. In this paper we propose a module generator, which uses a design constraint to achieve a flexible transistor sizing by a logic cell generation part. And generated logic cells can be easily adapted to layout generator. Almost all of these logic cells have 2-input. 2-input logic cells are implemented in place of conventional AND/OR planes. By using the 2-input logic cells, some classes of logic function can be implemented in a smaller circuit area. Also this module generator has a design rule interface part. With design rule interface part module generator acquires flexibility to process technologies, and module generator becomes adaptable to new process technologies. |
キーワード(和) | |
キーワード(英) | Module Generator / Dual-Rail PLA / 2-input Logic Cell / Design Rule Interface / Transistor Sizing |
資料番号 | VLD2002-152,ICD2002-217 |
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研究会情報 | |
研究会 | VLD |
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開催期間 | 2003/2/27(から1日開催) |
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申込み研究会 | VLSI Design Technologies (VLD) |
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本文の言語 | ENG |
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タイトル(英) | Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells |
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キーワード(1)(和/英) | / Module Generator |
第 1 著者 氏名(和/英) | / Ulkuhan Ekiniciel |
第 1 著者 所属(和/英) | Department of Electronic Engineering, The University of Tokyo |
発表年月日 | 2003/2/27 |
資料番号 | VLD2002-152,ICD2002-217 |
巻番号(vol) | vol.102 |
号番号(no) | 683 |
ページ範囲 | pp.- |
ページ数 | 6 |
発行日 |