Presentation 2003/1/22
Implementation of Discrete Wavelet Transform on DRP
Katsuaki DEGUCHI, Yutaka YAMADA, Hideharu AMANO,
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Abstract(in English) NEC's Dynamically Reconfigurable Processor (DRP) is a multicontext reconfigurable device consisting of eight individually reconfigurable units called "Tile." Data path configuration mapped to each tile can be selected from on-chip repository of sixteen circuit configurations, or contexts. The context switching can be done with a clock cycle. Using this mechanism, Daubechies wavelet filter whose length of filter can be changed is designed and implemented. Evaluation results show that the performance degradation caused by the variable length mechanism is not so large compared with a fixed length filter, and its absolute performance is comparable to those of software execution on recent high performance PCs.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) multicontext device / DRP / Discrete Wavelet Transfer / Daubechies
Paper # VLD20002-142,CPSY2002-95
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Committee VLD
Conference Date 2003/1/22(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation of Discrete Wavelet Transform on DRP
Sub Title (in English)
Keyword(1) multicontext device
Keyword(2) DRP
Keyword(3) Discrete Wavelet Transfer
Keyword(4) Daubechies
1st Author's Name Katsuaki DEGUCHI
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Yutaka YAMADA
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Hideharu AMANO
3rd Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2003/1/22
Paper # VLD20002-142,CPSY2002-95
Volume (vol) vol.102
Number (no) 609
Page pp.pp.-
#Pages 6
Date of Issue