| Presentation | 2003/1/21 Area Efficient FPGA Architecture with Logic Function Folding Hirotsugu KAJIHARA, Masaki NAKANISHI, Takashi HORIYAMA, Shinji KIMURA, Katsumasa WATANABE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The paper describes an area efficient FPGA architecture based on LUTs with logic function folding. Each LUT is a 3-1 LUT but is enhanced to implement a full adder function with only one LUT. The area of our 3-1 LUT is about 56 % compared to that of a simple 4-1 LUT. In the paper, we measure not only the LUT area but also the are aof routing resource. We adopt the well-known island style-architecture for the routing mechanism, and find that the total FPGA area can be saved up to 32.4 % and on average 12% by the experiments on several benchmark circuits compared to FPGA architecture based on 4-1 LUTs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA Architecture / Logic Function Folding / Look Up Table |
| Paper # | VLD2002-126,CPSY2002-79 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2003/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Area Efficient FPGA Architecture with Logic Function Folding |
| Sub Title (in English) | |
| Keyword(1) | FPGA Architecture |
| Keyword(2) | Logic Function Folding |
| Keyword(3) | Look Up Table |
| 1st Author's Name | Hirotsugu KAJIHARA |
| 1st Author's Affiliation | Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Masaki NAKANISHI |
| 2nd Author's Affiliation | Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Takashi HORIYAMA |
| 3rd Author's Affiliation | Informatics, Kyoto University |
| 4th Author's Name | Shinji KIMURA |
| 4th Author's Affiliation | Information, Production and systems, Waseda University |
| 5th Author's Name | Katsumasa WATANABE |
| 5th Author's Affiliation | Information Science, Nara Institute of Science and Technology |
| Date | 2003/1/21 |
| Paper # | VLD2002-126,CPSY2002-79 |
| Volume (vol) | vol.102 |
| Number (no) | 608 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |