| Presentation | 2002/11/21 Flexible Hardware Model : A Hardware Model for IP reuse and its Database Management System FHM-DBMS Yoshinori TAKEUCHI, Kyoto UEDA, Yukinori YAMANE, Akichika Shiomi, Masaharu IMAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This report introduces the Flexible Hardware Model for IP reuse design methodology in VLSI design. In conventional IP reuse design, IP's are often used with slight modifications in order to be introduced in the target system and becomes difficult to be reused. However, if a well considered component model for IP reuse is available, IP reuse design becomes more efficient. Flexible Hardware Model is proposed for targeting such a component model for IP reuse. This article introduces the concept of Flexible Hardware Model and its prototype database management system for FHM, first. Then, an example of FHM-DBMS usage is reported which is a resource database in ASIP Meister. ASIP Meister is an application specific instruction set processor design environment. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | IP reuse / Hardware Model / Database System / ASIP Meister |
| Paper # | VLD2002-119 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Flexible Hardware Model : A Hardware Model for IP reuse and its Database Management System FHM-DBMS |
| Sub Title (in English) | |
| Keyword(1) | IP reuse |
| Keyword(2) | Hardware Model |
| Keyword(3) | Database System |
| Keyword(4) | ASIP Meister |
| 1st Author's Name | Yoshinori TAKEUCHI |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Kyoto UEDA |
| 2nd Author's Affiliation | Graduate School of Engineering Sciece, Osaka University |
| 3rd Author's Name | Yukinori YAMANE |
| 3rd Author's Affiliation | Graduate School of Engineering Sciece, Osaka University |
| 4th Author's Name | Akichika Shiomi |
| 4th Author's Affiliation | School of Information, Shizuoka University |
| 5th Author's Name | Masaharu IMAI |
| 5th Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2002/11/21 |
| Paper # | VLD2002-119 |
| Volume (vol) | vol.102 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |