| Presentation | 2002/11/21 Consideration about IP Supply of Hardware Systems Utilizing Spec-Design CAD Kentaro YOSHIKAWA, Yoshikazu MIYANAGA, Shingo YOSHIZAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, a spec-design CAD is proposed as a new system which can freely generate a Verilog-HDL source file in the RTL stage. The HDL source is the design data of the circuit provided with functions and specification required by a user. A GUI is adopted as a user interface. The specification of the detail circuits generated is predicted beforehand and the information is fed back to a user immediately. Thereby, a setup of the design parameters is easily realized. This report focuses on the automatic generation of a DFT operation circuit as a simple example case of spec-design CAD and explains the structure of the parameter setup and its design data generation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DFT / RTL / Design Generation / High Level Synthesis / IP |
| Paper # | VLD2002-118 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Consideration about IP Supply of Hardware Systems Utilizing Spec-Design CAD |
| Sub Title (in English) | |
| Keyword(1) | DFT |
| Keyword(2) | RTL |
| Keyword(3) | Design Generation |
| Keyword(4) | High Level Synthesis |
| Keyword(5) | IP |
| 1st Author's Name | Kentaro YOSHIKAWA |
| 1st Author's Affiliation | Graduate School of Engineering, Hokkaido University() |
| 2nd Author's Name | Yoshikazu MIYANAGA |
| 2nd Author's Affiliation | Graduate School of Engineering, Hokkaido University |
| 3rd Author's Name | Shingo YOSHIZAWA |
| 3rd Author's Affiliation | Graduate School of Engineering, Hokkaido University |
| Date | 2002/11/21 |
| Paper # | VLD2002-118 |
| Volume (vol) | vol.102 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |