Presentation 2002/11/21
Development of Multiplier and Divider IPs
Tomohide MIZUNO, Masayuki SHINOHARA, Kazuyoshi TAKAGI, Naofumi TAKAGI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) To be used as IP (Intellectual Property), we have designed multipliers and deviders. We have designed two 32-bit multipliers; one based on Wallace tree which is known to have the minimum curcuit stage, and the other on Overturned-Stairs tree which has more stages but a regular structure. We have designed dividers calculating the significand in IEEE 754 single precision format. We have implemented a radix-2 and a radix-4 divider, as well as a divider with overlapped radix-2 digit selection. We have also designed each divider with retiming.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) IP / Multiplier / Overturned-Stairs tree / Wallace tree / Divider / Overlapping digit selection
Paper # VLD2002-115
Date of Issue

Conference Information
Committee VLD
Conference Date 2002/11/21(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Multiplier and Divider IPs
Sub Title (in English)
Keyword(1) IP
Keyword(2) Multiplier
Keyword(3) Overturned-Stairs tree
Keyword(4) Wallace tree
Keyword(5) Divider
Keyword(6) Overlapping digit selection
1st Author's Name Tomohide MIZUNO
1st Author's Affiliation Department of Information Engineering, Nagoya University()
2nd Author's Name Masayuki SHINOHARA
2nd Author's Affiliation Department of Information Engineering, Nagoya University
3rd Author's Name Kazuyoshi TAKAGI
3rd Author's Affiliation Department of Information Engineering, Nagoya University
4th Author's Name Naofumi TAKAGI
4th Author's Affiliation Department of Information Engineering, Nagoya University
Date 2002/11/21
Paper # VLD2002-115
Volume (vol) vol.102
Number (no) 476
Page pp.pp.-
#Pages 6
Date of Issue