Presentation | 2002/11/21 Soft-core Processor with MIPS R3000 Compatible Instruction Set and its Applications Tetsuo HIRONAKA, Takahiro SASAKI, Naoki NISHIMURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We developed a soft-core processor IP which has instruction set compatibility with the MIPS R3000 processor. This soft-core processor can be used as IP for developing SOC (System on Chip). The soft-core processor was developed independently from companies which are related to the R3000 processor, so the developed processor do not include any design data and technical aid from these companies including the MIPS corporation. This paper introduces the details of the soft-core processor IP, and research and developments on on-chip multi-processors using this IP. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Soft-core Processor / IP / On Chip Multiprocessor |
Paper # | VLD2002-114 |
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Committee | VLD |
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Conference Date | 2002/11/21(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Soft-core Processor with MIPS R3000 Compatible Instruction Set and its Applications |
Sub Title (in English) | |
Keyword(1) | Soft-core Processor |
Keyword(2) | IP |
Keyword(3) | On Chip Multiprocessor |
1st Author's Name | Tetsuo HIRONAKA |
1st Author's Affiliation | Faculty of Information Sciences, Hiroshima City University() |
2nd Author's Name | Takahiro SASAKI |
2nd Author's Affiliation | Faculty of Information Sciences, Hiroshima City University |
3rd Author's Name | Naoki NISHIMURA |
3rd Author's Affiliation | (Present address)Sony LSI Design Inc. |
Date | 2002/11/21 |
Paper # | VLD2002-114 |
Volume (vol) | vol.102 |
Number (no) | 476 |
Page | pp.pp.- |
#Pages | 6 |
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