| Presentation | 2002/11/21 A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search Yuji YANO, Masahiro MIZOKAMI, Minoru HONDA, Tetsushi KOIDE, Hans Jurgen MATTAUSCH, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Finding the nearest-match between an input-data word of k * W bit length and a number R of reference-data words is a basic operation for pattern recognition as well as data compression. Further, it is important for future advanced intelligent imformation processing to realize this nearest-match functionality with fast and compact hardware. This paper presents a mixed-analog-digital asociative memory which uses a fully-parallel processing architecture. The proposed associative memory performs high speed nearest-match search, in which digital processing is used up to the word comparison and analog processing is used for the winner-take-all function. A test chip was designed in 0.35μm CMOS technology with 3-metal layers. The nearest-match unit consumes 0.99mm^2 (11.5% of total design area), while the chip area is 8.6mm^2. The simulated winner-search time of this chip, the time to determine the best-matching reference-data word for an input-data word among a database of 128 reference words (5-bit, 16 units), is lower than 240nsec. This corresponds to a performance requirement of 20 GOPS/mm^2, if a 32-bit computer with the same chip area would have to run the same workload. Furthermore the power dissipation of the designed test chip is only about 30.2mW/mm^2. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | mixed-digital-analog circuits / associative memory / Manhattan distance / fully-parallel search / pattern recognition |
| Paper # | VLD2002-112 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Fully-Parallel Associative Memory for Minimum-Manhattan-Distance-Search |
| Sub Title (in English) | |
| Keyword(1) | mixed-digital-analog circuits |
| Keyword(2) | associative memory |
| Keyword(3) | Manhattan distance |
| Keyword(4) | fully-parallel search |
| Keyword(5) | pattern recognition |
| 1st Author's Name | Yuji YANO |
| 1st Author's Affiliation | Research center for Nanodevices and Systems, Hiroshima University() |
| 2nd Author's Name | Masahiro MIZOKAMI |
| 2nd Author's Affiliation | Research center for Nanodevices and Systems, Hiroshima University |
| 3rd Author's Name | Minoru HONDA |
| 3rd Author's Affiliation | Research center for Nanodevices and Systems, Hiroshima University |
| 4th Author's Name | Tetsushi KOIDE |
| 4th Author's Affiliation | Research center for Nanodevices and Systems, Hiroshima University |
| 5th Author's Name | Hans Jurgen MATTAUSCH |
| 5th Author's Affiliation | Research center for Nanodevices and Systems, Hiroshima University |
| Date | 2002/11/21 |
| Paper # | VLD2002-112 |
| Volume (vol) | vol.102 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |