| Presentation | 2002/11/21 Multi-Port-Cache Design with Hierarchical Multi-Bank Memory Koh JOHGUCHI, Zhaomin ZHU, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Tai HIRAKAWA, Tetsuo HIRONAKA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, there has been a high demand for parallelism of computers. Large capacity and high bandwidth of the cache are needed for this demand. Therefore, we proposed to apply the Hierarchical Multi-port memory Architechture (HMA), which offers both high bandwidth and small area. In this paper, a HMA-cache-design example with 4 ports in a 0.18μm CMOS technology with 5 metal layers and an integration concept for data and instruction cache is introduced. The capacity of the banks in the design example is 1KB and the word length is 32bits. Due to chip-space limitations we had to restrict this design to 4 banks. The simulated access time of a bank in the test chip is 2.2ns. We could reduce the access time afterwards to 1.2ns by optimizing the critical path. A Unification method for instruction/data cache, which becomes possible with a small-area multi-port cache, consisting of multiple 1-port banks, is also discussed in this paper. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-port memory / multi-bank / cache / unified cache / integrated cache / superscalar |
| Paper # | VLD2002-110 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Multi-Port-Cache Design with Hierarchical Multi-Bank Memory |
| Sub Title (in English) | |
| Keyword(1) | multi-port memory |
| Keyword(2) | multi-bank |
| Keyword(3) | cache |
| Keyword(4) | unified cache |
| Keyword(5) | integrated cache |
| Keyword(6) | superscalar |
| 1st Author's Name | Koh JOHGUCHI |
| 1st Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University() |
| 2nd Author's Name | Zhaomin ZHU |
| 2nd Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 3rd Author's Name | Hans Jurgen MATTAUSCH |
| 3rd Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 4th Author's Name | Tetsushi KOIDE |
| 4th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 5th Author's Name | Tai HIRAKAWA |
| 5th Author's Affiliation | Faculty of Computer Sciences, Hiroshima City University |
| 6th Author's Name | Tetsuo HIRONAKA |
| 6th Author's Affiliation | Faculty of Computer Sciences, Hiroshima City University |
| Date | 2002/11/21 |
| Paper # | VLD2002-110 |
| Volume (vol) | vol.102 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |