Presentation 2002/11/21
A Modulo M Multiplier/Divider
Marcelo E. KAIHARA, Naofumi TAKAGI,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose a modulo M multiplier/divider which is suitable for VLSI realization. It is based on our newly proposed combined algorithm for modular multiplication and division. The modular multiplication is based on Montgomery's method and the modular division on the extended Binary GCD algorithm. Both calculations are carried out through iteration of simple operations such as shifts and addition/subtractions. The radix-2 signed-digit representation is employed so that all additions and subtractions are performed without carry propagation. The modulo M multiplier/divider has a linear array structure with a bit-slice feature and carries out n-bit modulo M multiplication/division in O(n) clock cycles, where the length of the clock cycle is constant and independent of n.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) modular arithmetic / modular multiplication / modular division / Montogomery's algorithm / extended binary GCD algorithm / hardware algorithm / VLSI algorithm
Paper # VLD2002-109
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Committee VLD
Conference Date 2002/11/21(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Modulo M Multiplier/Divider
Sub Title (in English)
Keyword(1) modular arithmetic
Keyword(2) modular multiplication
Keyword(3) modular division
Keyword(4) Montogomery's algorithm
Keyword(5) extended binary GCD algorithm
Keyword(6) hardware algorithm
Keyword(7) VLSI algorithm
1st Author's Name Marcelo E. KAIHARA
1st Author's Affiliation Department of Information Engineering, Nagoya University()
2nd Author's Name Naofumi TAKAGI
2nd Author's Affiliation Department of Information Engineering, Nagoya University
Date 2002/11/21
Paper # VLD2002-109
Volume (vol) vol.102
Number (no) 476
Page pp.pp.-
#Pages 6
Date of Issue