Presentation | 2002/11/21 A Modulo M Multiplier/Divider Marcelo E. KAIHARA, Naofumi TAKAGI, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We propose a modulo M multiplier/divider which is suitable for VLSI realization. It is based on our newly proposed combined algorithm for modular multiplication and division. The modular multiplication is based on Montgomery's method and the modular division on the extended Binary GCD algorithm. Both calculations are carried out through iteration of simple operations such as shifts and addition/subtractions. The radix-2 signed-digit representation is employed so that all additions and subtractions are performed without carry propagation. The modulo M multiplier/divider has a linear array structure with a bit-slice feature and carries out n-bit modulo M multiplication/division in O(n) clock cycles, where the length of the clock cycle is constant and independent of n. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | modular arithmetic / modular multiplication / modular division / Montogomery's algorithm / extended binary GCD algorithm / hardware algorithm / VLSI algorithm |
Paper # | VLD2002-109 |
Date of Issue |
Conference Information | |
Committee | VLD |
---|---|
Conference Date | 2002/11/21(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
---|---|
Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Modulo M Multiplier/Divider |
Sub Title (in English) | |
Keyword(1) | modular arithmetic |
Keyword(2) | modular multiplication |
Keyword(3) | modular division |
Keyword(4) | Montogomery's algorithm |
Keyword(5) | extended binary GCD algorithm |
Keyword(6) | hardware algorithm |
Keyword(7) | VLSI algorithm |
1st Author's Name | Marcelo E. KAIHARA |
1st Author's Affiliation | Department of Information Engineering, Nagoya University() |
2nd Author's Name | Naofumi TAKAGI |
2nd Author's Affiliation | Department of Information Engineering, Nagoya University |
Date | 2002/11/21 |
Paper # | VLD2002-109 |
Volume (vol) | vol.102 |
Number (no) | 476 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |