Presentation | 2002/11/21 High-Speed Modular Arithmetic Accelerator for RSA Public Key Cryptosystem Yuhki KAJIWARA, Makoto NAGATA, Kazuo TAKI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We designed a high-speed modular exponentiation unit for RSA cryptosystem, which is one of the most representative public key cryptosystems. For acceleration, we tried to reduce clock cycles for the calculation, and now we developed an algorithm appropriately combining two efficient algorithms, that are called Left-to-Right k-ary method and Montgomery multiplication. We also tried to reduce the cycle time by dividing the critical-path in the unit. We have the result that the unit can calculate a 1024 bit modular exponentiation for 3.2 ms. This unit has high-speed capability and implementable size on an LSI chip. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | RSA cryptosystem / Left-to-Right k-ary method / Montgomery multiplication / Reducing clock cycles |
Paper # | VLD2002-108 |
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Committee | VLD |
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Conference Date | 2002/11/21(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | High-Speed Modular Arithmetic Accelerator for RSA Public Key Cryptosystem |
Sub Title (in English) | |
Keyword(1) | RSA cryptosystem |
Keyword(2) | Left-to-Right k-ary method |
Keyword(3) | Montgomery multiplication |
Keyword(4) | Reducing clock cycles |
1st Author's Name | Yuhki KAJIWARA |
1st Author's Affiliation | Graduate School of Science and Technology, Kobe University() |
2nd Author's Name | Makoto NAGATA |
2nd Author's Affiliation | Department of Computer and Systems Engineering, Kobe University |
3rd Author's Name | Kazuo TAKI |
3rd Author's Affiliation | AIL Co.,Ltd. |
Date | 2002/11/21 |
Paper # | VLD2002-108 |
Volume (vol) | vol.102 |
Number (no) | 476 |
Page | pp.pp.- |
#Pages | 6 |
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