Presentation 2002/11/21
A Processor System for Embedded Control System on FPGA
Hideo ARAKI, Toshiro KUTSUWA, Katsumi HARASHIMA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) FPGA is an essential device to design of hardware at present. The applying ways have been studying actively for the system design problem caused by its capacity expansion, large scaling and speed-up in recent years. One of the applying ways is "SoC". It is a design method to include all of requirements on a VLSI-chip. FPGA is a re-configurable LSI device. We apply the design method for a FPGA design. To build micro-processors applied system on a FPGA, a lot of micro-processors is specified and to difficult building the software for them. The most difficult deign of the software is to build an OS (Operation System). To design an OS consumes time and labor. We develop a micro-processor to implement an OS easily for embedded systems.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / SoC (System on a Chip) / Embedded System / Real-time / Multi Processor
Paper # VLD2002-105
Date of Issue

Conference Information
Committee VLD
Conference Date 2002/11/21(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Processor System for Embedded Control System on FPGA
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) SoC (System on a Chip)
Keyword(3) Embedded System
Keyword(4) Real-time
Keyword(5) Multi Processor
1st Author's Name Hideo ARAKI
1st Author's Affiliation Faculty of Engineering, Osaka Institute of Technology()
2nd Author's Name Toshiro KUTSUWA
2nd Author's Affiliation Faculty of Engineering, Osaka Institute of Technology
3rd Author's Name Katsumi HARASHIMA
3rd Author's Affiliation Faculty of Engineering, Osaka Institute of Technology
Date 2002/11/21
Paper # VLD2002-105
Volume (vol) vol.102
Number (no) 476
Page pp.pp.-
#Pages 5
Date of Issue