| Presentation | 2002/11/21 Implementation of Protocol Booster with Dynamically Reconfigurable System Kazunori SHIMIZU, Chen XIAOMEI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, dynamical reconfigurable devices or systems whose circuits can be configured during the operation are attracting the attention. Circuit size can be enlarged virtually on the dynamic reconfigurable system, and that makes high-speed process possible with a small amount of hardware resources. In this report, we employ protocol boosters as an application on a dynamical reconfigurable system and implement it with our dynamical reconfigurable FPGA system. A protocol booster is a program, which adds several functions to network nodes and executes an encode and/or decode process applicable to each input packet. It may be slow if these encode/decode processes are implemented with software, or an individual hardware must be provided for each process if all of these processes are implemented with hardware. By implementing the protocol boosters with our dynamic reconfigurable system, any type of encode/decode process can be operated for packets on the network at a high speed within the limited cost. Experimental results show the effectiveness of our dynamic reconfigurable system for protocol boosters. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | dynamic reconfigurabale system / Protocol Booster / FPGA / code-process |
| Paper # | VLD2002-103 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Protocol Booster with Dynamically Reconfigurable System |
| Sub Title (in English) | |
| Keyword(1) | dynamic reconfigurabale system |
| Keyword(2) | Protocol Booster |
| Keyword(3) | FPGA |
| Keyword(4) | code-process |
| 1st Author's Name | Kazunori SHIMIZU |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University() |
| 2nd Author's Name | Chen XIAOMEI |
| 2nd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Information and Media Sciences, The University of Kitakyushu:Advanced Research Institute for Science and Engineering, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University |
| Date | 2002/11/21 |
| Paper # | VLD2002-103 |
| Volume (vol) | vol.102 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |