Presentation 2002/11/21
Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits
Makoto NAGATA, Takashi MORIE, Atsushi IWATA,
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Abstract(in English) A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in time domain. The simulation of a 0.25-μm z80 micro-controller with 62.5-MHz clock frequency costs less than 10 sec. per a clock cycle including the model generation. Simulated substrate noise well consists with 200-ps 100-μV resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows the peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Substrate noise / Power-supply noise / Power-supply current modeling / Crosstalk
Paper # VLD2002-93
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Committee VLD
Conference Date 2002/11/21(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits
Sub Title (in English)
Keyword(1) Substrate noise
Keyword(2) Power-supply noise
Keyword(3) Power-supply current modeling
Keyword(4) Crosstalk
1st Author's Name Makoto NAGATA
1st Author's Affiliation Department of Computer and Systems Engineering, Kobe University()
2nd Author's Name Takashi MORIE
2nd Author's Affiliation Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology
3rd Author's Name Atsushi IWATA
3rd Author's Affiliation Graduate School of Advanced Sciences of Matter, Hiroshima University
Date 2002/11/21
Paper # VLD2002-93
Volume (vol) vol.102
Number (no) 476
Page pp.pp.-
#Pages 5
Date of Issue