| Presentation | 2002/6/22 Construction of Processing Environment with FPGAs and DSPs Yuhei HAYASHI, Yuichi IWAYA, Koichiro TANAKA, Toshinori SATO, Itsujiro ARITA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper reports the processing environment on RYUOH, which is an original hardware platform for studying reconfigurable computing, and its evaluation result by the JPEG encoder. As density of LSI circuits increases, the time required for their development and verification also increases. LSIs including a high flexibility will solve the problem. RYUOH consists of an FPGA, a DSP and a DIMM. In order to evaluate RYUOH, JPEG encoder is implemented in each device. As a result, the bandwidths between FPGA and DSP are 7.68MB/s with asynchronous interface and 42.6MB/s with synchronous interface, when the JPEG encoder is running on RYUOH. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable Computing / Cooperative Processing / FPGA / DSP |
| Paper # | VLD2002-59 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/6/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Construction of Processing Environment with FPGAs and DSPs |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable Computing |
| Keyword(2) | Cooperative Processing |
| Keyword(3) | FPGA |
| Keyword(4) | DSP |
| 1st Author's Name | Yuhei HAYASHI |
| 1st Author's Affiliation | Department of Artifical Intelligence, Kyushu Institute of Technology() |
| 2nd Author's Name | Yuichi IWAYA |
| 2nd Author's Affiliation | Department of Artifical Intelligence, Kyushu Institute of Technology |
| 3rd Author's Name | Koichiro TANAKA |
| 3rd Author's Affiliation | Center for Microelectronic Systems, Kyushu Institute of Technology |
| 4th Author's Name | Toshinori SATO |
| 4th Author's Affiliation | Department of Artifical Intelligence, Kyushu Institute of Technology:Center for Microelectronic Systems, Kyushu Institute of Technology |
| 5th Author's Name | Itsujiro ARITA |
| 5th Author's Affiliation | Department of Artifical Intelligence, Kyushu Institute of Technology |
| Date | 2002/6/22 |
| Paper # | VLD2002-59 |
| Volume (vol) | vol.102 |
| Number (no) | 166 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |