| Presentation | 2002/6/22 Method for Phase-Assignment in Automatic Phase-Shift Mask Design Keitaro Katabuchi, Eiji Tsujimoto, Akemi Moniwa, Takuya Hagiwara, Yosinobu Igarashi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The phase-shift mask is used for resolving gate pattern, which requires pattern fidelity. In the phase-shift mask, which is resolution enhancement technology to improve pattern fidelity, phase-shifters reverse the light's phase on one of the apertures of adjacent apertures so that the two lights interfere destructively and their intensity reduces sharply to transcribe gate patterns. Usually, the phase-assignment software assigns opposite phase for any pairs of aperture when gates are arranged regularly. But when the layout is arranged irregularly, a pair of adjacent aperture may be assigned in the same phase, and it diminishes the gate pattern fidelity around such apertures. But almost all of automatic phase-shifter placement software does not take this case into consideration. In this paper, we describe the method to assign all of adjacent aperture pair in different phase for irregular gate layout. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | resolution enhancement technology / phase-shift mask / pattern fidelity / phase-assignment |
| Paper # | VLD2002-58 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/6/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Method for Phase-Assignment in Automatic Phase-Shift Mask Design |
| Sub Title (in English) | |
| Keyword(1) | resolution enhancement technology |
| Keyword(2) | phase-shift mask |
| Keyword(3) | pattern fidelity |
| Keyword(4) | phase-assignment |
| 1st Author's Name | Keitaro Katabuchi |
| 1st Author's Affiliation | Hitachi, Ltd., Device Development Center() |
| 2nd Author's Name | Eiji Tsujimoto |
| 2nd Author's Affiliation | Hitachi, Ltd., Device Development Center |
| 3rd Author's Name | Akemi Moniwa |
| 3rd Author's Affiliation | Hitachi, Ltd., Semiconductor & Integrated Circuit Division |
| 4th Author's Name | Takuya Hagiwara |
| 4th Author's Affiliation | Hitachi, Ltd., Center Research Laboratory |
| 5th Author's Name | Yosinobu Igarashi |
| 5th Author's Affiliation | Hitachi, Ltd., Semiconductor & Integrated Circuit Division |
| Date | 2002/6/22 |
| Paper # | VLD2002-58 |
| Volume (vol) | vol.102 |
| Number (no) | 166 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |