| Presentation | 2002/6/21 Design of a Compact PLL with New Active Loop Filter Circuit Shiro Dosho, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes the design of a new active low pass filter for Phase-Locked-Loop(PLL) with adaptive biasing technique. Using the new low pass filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10 of the conventional one. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Phase-Locked-Loops / Active Filter / Adaptive Bias / Miniaturization / CMOS |
| Paper # | VLD2002-46 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/6/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a Compact PLL with New Active Loop Filter Circuit |
| Sub Title (in English) | |
| Keyword(1) | Phase-Locked-Loops |
| Keyword(2) | Active Filter |
| Keyword(3) | Adaptive Bias |
| Keyword(4) | Miniaturization |
| Keyword(5) | CMOS |
| 1st Author's Name | Shiro Dosho |
| 1st Author's Affiliation | Advanced LSI Technology Development Center Corporate Development Division, Semiconductor Company Matsushita Electric Industrial Co.Ltd.() |
| Date | 2002/6/21 |
| Paper # | VLD2002-46 |
| Volume (vol) | vol.102 |
| Number (no) | 165 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |