| Presentation | 2002/6/21 Architecture of Pseudo Random Noise Code Generator for Next-Generation GNSS Receiver Tsutomu OKADA, Tsubasa UCHIDA, Takao ONOYE, Isao SHIRAKAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As a solution over the application field, which requires higher performance far more than that of existing GPS (Global Positioning System), GNSS (Global Navigation Satellite System) receiver compliant to two or more satellite navigation systems is being developed. In this paper, a novel architecture of a next generation GNSS receiver is devised with the main theme focused on constructing the detailed structure and its control method of a general purpose PRN (Pseudo Random Noise) code generator. Employing a pair of feedback shift registers with efficient phase control capabilities for PRN codes, the proposed architecture greatly reduces required hardware resources of the general purpose PRN code generator. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | GNSS / GPS / GLONASS / Satellite Navigation System / Receiver / Pseudo Random Noise Code |
| Paper # | VLD2002-43 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2002/6/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Architecture of Pseudo Random Noise Code Generator for Next-Generation GNSS Receiver |
| Sub Title (in English) | |
| Keyword(1) | GNSS |
| Keyword(2) | GPS |
| Keyword(3) | GLONASS |
| Keyword(4) | Satellite Navigation System |
| Keyword(5) | Receiver |
| Keyword(6) | Pseudo Random Noise Code |
| 1st Author's Name | Tsutomu OKADA |
| 1st Author's Affiliation | Department of Information Systems Engineering, Osaka University:Researching Office 3, Researching Dept., Furuno Electric Co., Ltd.() |
| 2nd Author's Name | Tsubasa UCHIDA |
| 2nd Author's Affiliation | Department of Information Networking, Osaka University |
| 3rd Author's Name | Takao ONOYE |
| 3rd Author's Affiliation | Department of Information Systems Engineering, Osaka University |
| 4th Author's Name | Isao SHIRAKAWA |
| 4th Author's Affiliation | Department of Information Systems Engineering, Osaka University |
| Date | 2002/6/21 |
| Paper # | VLD2002-43 |
| Volume (vol) | vol.102 |
| Number (no) | 165 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |