| Presentation | 2004/5/14 Full-Rate architecture 16:1 Multiplexer and 1:16 Demultiplexer with integrated 39.8 to 43GHz VCO for OC-768 communication systems Keiki WATANABE, Akio KOYAMA, Tatsuhiro AIDA, Hiroyuki YOSHIOKA, Hiroki YAMASHITA, Masahiro ITO, Nobuhiro SHIRAMIZU, Takahiro NAKAMURA, Hiroyuki CHIBA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A fully integrated 39.8 to 43Gb/s OC-768 16:1 Multiplexer (MUX) / Demultiplexer (DEMUX) chipset is implemented in a 0.1 Sum BiCMOS process. Full-rate operation is realized with on-chip VCO. The measured output jitter of packaged MUX is 630fs-rms and the sensitivity of DEMUX is 31mVpp single-ended with a BER < 10^<-12>. The chipset dissipates 11.6W. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multiplexer / Demuliplexer / 39.8-43Gb/s / Full-Rate architecture / SiGe BiCMOS |
| Paper # | ICD2004-35 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/5/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Full-Rate architecture 16:1 Multiplexer and 1:16 Demultiplexer with integrated 39.8 to 43GHz VCO for OC-768 communication systems |
| Sub Title (in English) | |
| Keyword(1) | Multiplexer |
| Keyword(2) | Demuliplexer |
| Keyword(3) | 39.8-43Gb/s |
| Keyword(4) | Full-Rate architecture |
| Keyword(5) | SiGe BiCMOS |
| 1st Author's Name | Keiki WATANABE |
| 1st Author's Affiliation | Micro Device Division, Hitachi, Ltd.() |
| 2nd Author's Name | Akio KOYAMA |
| 2nd Author's Affiliation | Micro Device Division, Hitachi, Ltd. |
| 3rd Author's Name | Tatsuhiro AIDA |
| 3rd Author's Affiliation | Micro Device Division, Hitachi, Ltd. |
| 4th Author's Name | Hiroyuki YOSHIOKA |
| 4th Author's Affiliation | Micro Device Division, Hitachi, Ltd. |
| 5th Author's Name | Hiroki YAMASHITA |
| 5th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 6th Author's Name | Masahiro ITO |
| 6th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 7th Author's Name | Nobuhiro SHIRAMIZU |
| 7th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 8th Author's Name | Takahiro NAKAMURA |
| 8th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 9th Author's Name | Hiroyuki CHIBA |
| 9th Author's Affiliation | Hitachi ULSI Systems Co., Ltd. |
| Date | 2004/5/14 |
| Paper # | ICD2004-35 |
| Volume (vol) | vol.104 |
| Number (no) | 67 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |