| Presentation | 2004/9/3 Security of Integrated Circuits: Immunity Against Tampering by Using Failure Analysis Techniques (II) : Process Technologies To Increase Tampering Immunity of LSIs Shigeru NAKAJIMA, Tadashi SHIBATA, Atsuhiro YAMAGISHI, Tsutomu MATSMOTO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Based on consideration for weak points of failure analysis techniques, vertical and horizontal structures which may increase tamparing immunity of the LSI are described. To prevent analysis using the emission microscopy, optimization of device structures and bias conditions for reducing internal electric field of MOSFETs is effective because only week light is emitted from MOSFET with low internal electric field. To prevent waveform measurement using non-contact testing methos such as electron beam testing, placement of noisy interconnections between signal lines is effective. To prevent analysis from backside, formation of highly doped layers in near upper part of silicon crystal is effective because infrared ray is absorbed in highly doped layers. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | integrated circuit / LSI / security / decription / tampering immunity / failure analysis |
| Paper # | ICD2004-106 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/9/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Security of Integrated Circuits: Immunity Against Tampering by Using Failure Analysis Techniques (II) : Process Technologies To Increase Tampering Immunity of LSIs |
| Sub Title (in English) | |
| Keyword(1) | integrated circuit |
| Keyword(2) | LSI |
| Keyword(3) | security |
| Keyword(4) | decription |
| Keyword(5) | tampering immunity |
| Keyword(6) | failure analysis |
| 1st Author's Name | Shigeru NAKAJIMA |
| 1st Author's Affiliation | Van Partners Corpolation() |
| 2nd Author's Name | Tadashi SHIBATA |
| 2nd Author's Affiliation | School of Frontier Sciences, University of Tokyo |
| 3rd Author's Name | Atsuhiro YAMAGISHI |
| 3rd Author's Affiliation | Information-Technology Promotion Agency |
| 4th Author's Name | Tsutomu MATSMOTO |
| 4th Author's Affiliation | Graduate School of Environment and Information Sciences, Yokohama National University |
| Date | 2004/9/3 |
| Paper # | ICD2004-106 |
| Volume (vol) | vol.104 |
| Number (no) | 288 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |