| Presentation | 2004/9/3 Low-Power Field-Programmable VLSI Using Multiple Supply Voltages Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a low-power field-programmable VLSI processor (FPVLSI) to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). Large power consumption in FPGAs is mainly caused by complex routing networks. To reduce the complexity of routing networks, an area-efficient bit-serial pipeline architecture is introduced in the FPVLSI. A fine-grain supply-voltage-control scheme is proposed where a supply voltage of each logic block is programmable. To realize the scheme in an area-efficient way, a level-converter-less logic block using dynamic circuits is presented. The FPVLSI is evaluated based on a 0.18-^m CMOS design rule. The power consumption of the FPVLSI is reduced to 40% compared to that of the FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable processor / bit-serial architecture / multiple-supplv-voltage scheme |
| Paper # | ICD2004-100 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/9/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-Power Field-Programmable VLSI Using Multiple Supply Voltages |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable processor |
| Keyword(2) | bit-serial architecture |
| Keyword(3) | multiple-supplv-voltage scheme |
| 1st Author's Name | Weisheng CHONG |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Masanori HARIYAMA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Michitaka KAMEYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2004/9/3 |
| Paper # | ICD2004-100 |
| Volume (vol) | vol.104 |
| Number (no) | 288 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |