Presentation 2004/8/12
QUASI-PARALLEL MULTI-PATH DETECTION ARCHITECTURE USING FLOATING-GATE-MOS-BASED CDMA MATCHED FILTERS
Tomoyuki NAKAYAMA, Toshihiko YAMASAKI, Tadashi SHIBATA,
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Abstract(in English) A quasi-parallel matching architecture for CDMA matched filters has been proposed aiming at high-speed and flexible multi-path detection. In the architecture, a drastic reduction in the hardware volume has been achieved as compared with the fully-parallel matching architecture in Ref. [1], while preserving the equivalent performance. The feasibility of the chip implementation has been examined based on the experimental results obtained from the floating-gate-MOS matched filters fabricated in a 0.35-υm CMOS technology. As a result, the system is estimated to dissipate 15.5mW occupying 2mm^2 chip area for the 512-chip length correlation at a rate of 4.096Mchip/s.
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Keyword(in English) CDMA / Matched Filter / Multi-Path / Floating-Gate-MOS
Paper # SDM2004-137,ICD2004-79
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Conference Date 2004/8/12(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) QUASI-PARALLEL MULTI-PATH DETECTION ARCHITECTURE USING FLOATING-GATE-MOS-BASED CDMA MATCHED FILTERS
Sub Title (in English)
Keyword(1) CDMA
Keyword(2) Matched Filter
Keyword(3) Multi-Path
Keyword(4) Floating-Gate-MOS
1st Author's Name Tomoyuki NAKAYAMA
1st Author's Affiliation Department of Frontier Informatics, Graduate School of Frontier Sciences The University of Tokyo()
2nd Author's Name Toshihiko YAMASAKI
2nd Author's Affiliation Department of Frontier Informatics, Graduate School of Frontier Sciences The University of Tokyo
3rd Author's Name Tadashi SHIBATA
3rd Author's Affiliation Department of Frontier Informatics, Graduate School of Frontier Sciences The University of Tokyo
Date 2004/8/12
Paper # SDM2004-137,ICD2004-79
Volume (vol) vol.104
Number (no) 250
Page pp.pp.-
#Pages 6
Date of Issue