| Presentation | 2004/8/12 Lowpower Bluetooth Singlechip LSI : Circuit/Architecture/System Level Power Optimizations Mototsugu HAMADA, Hiroki ISHIKURO, Ken-ichi AGAWA, Shouhei KOUSAI, Hiroyuki KOBAYASHI, Duc NGUYEN, Yoshimitsu SHIMOJO, Fumitoshi HATORI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We report circuit/architecture/system-level power optimization of wireless LSI. As an illustration, we show a single-chip transceiver compliant with the Bluetooth ver.1.1 developed by using a 0.18μm CMOS technology. The chip contains RF circuits, baseband circuits, MPU, RAM, and ROM. For the optimization of a image rejection and a channel selection, a 1.5MHz intermediate frequency is selected in the Low-IF receiver. A direct modulation of a 2.4GHz VCO simplifies the transmitter circuits and reduces the current consumption. Fine controls of the radio part by the baseband digital circuits achieve a fast (6μsec) and stable gain control of the receiver and a fast lockup (85μsec) of the PLL while having a low phase noise (-130dBc/HZ @3MHz). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Single-Chip Transceiver / CMOS / RF / Bluetooth / Low-IF / Direct Modulation |
| Paper # | SDM2004-134,ICD2004-76 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/8/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Lowpower Bluetooth Singlechip LSI : Circuit/Architecture/System Level Power Optimizations |
| Sub Title (in English) | |
| Keyword(1) | Single-Chip Transceiver |
| Keyword(2) | CMOS |
| Keyword(3) | RF |
| Keyword(4) | Bluetooth |
| Keyword(5) | Low-IF |
| Keyword(6) | Direct Modulation |
| 1st Author's Name | Mototsugu HAMADA |
| 1st Author's Affiliation | SoC Research & Development Center, Toshiba Corp.() |
| 2nd Author's Name | Hiroki ISHIKURO |
| 2nd Author's Affiliation | SoC Research & Development Center, Toshiba Corp. |
| 3rd Author's Name | Ken-ichi AGAWA |
| 3rd Author's Affiliation | SoC Research & Development Center, Toshiba Corp. |
| 4th Author's Name | Shouhei KOUSAI |
| 4th Author's Affiliation | SoC Research & Development Center, Toshiba Corp. |
| 5th Author's Name | Hiroyuki KOBAYASHI |
| 5th Author's Affiliation | SoC Research & Development Center, Toshiba Corp. |
| 6th Author's Name | Duc NGUYEN |
| 6th Author's Affiliation | SoC Research & Development Center, Toshiba Corp. |
| 7th Author's Name | Yoshimitsu SHIMOJO |
| 7th Author's Affiliation | SoC Research & Development Center, Toshiba Corp. |
| 8th Author's Name | Fumitoshi HATORI |
| 8th Author's Affiliation | SoC Research & Development Center, Toshiba Corp. |
| Date | 2004/8/12 |
| Paper # | SDM2004-134,ICD2004-76 |
| Volume (vol) | vol.104 |
| Number (no) | 250 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |