Presentation 2004/8/12
Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect
Noriyuki MIURA, Daisuke MIZOGUCHI, Yusmeeraz Binti YUSOF, Takayasu SAKURAI, Tadahiro KURODA,
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Abstract(in English) A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. A test chip was fabricated in 0.35μm CMOS. Accuracy of the models is verified. The maximum data rate is 1.25Gb/s/channel.
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Keyword(in English) wireless bus / inductor / high bandwidth / low power / SiP
Paper # SDM2004-132,ICD2004-74
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Conference Date 2004/8/12(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect
Sub Title (in English)
Keyword(1) wireless bus
Keyword(2) inductor
Keyword(3) high bandwidth
Keyword(4) low power
Keyword(5) SiP
1st Author's Name Noriyuki MIURA
1st Author's Affiliation Department of Electronics and Electrical Engineering, Keio University()
2nd Author's Name Daisuke MIZOGUCHI
2nd Author's Affiliation Department of Electronics and Electrical Engineering, Keio University
3rd Author's Name Yusmeeraz Binti YUSOF
3rd Author's Affiliation Department of Electronics and Electrical Engineering, Keio University
4th Author's Name Takayasu SAKURAI
4th Author's Affiliation Center for Collaborative Research, The University of Tokyo
5th Author's Name Tadahiro KURODA
5th Author's Affiliation Department of Electronics and Electrical Engineering, Keio University
Date 2004/8/12
Paper # SDM2004-132,ICD2004-74
Volume (vol) vol.104
Number (no) 250
Page pp.pp.-
#Pages 6
Date of Issue