Presentation 2004/8/12
A Pixel-Parallel Gabor Filtering LSI Based on Merged Analog/Digital Architecture
Takashi MORIE, Jun UMEZAWA, Atsushi IWATA,
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Abstract(in English) Gabor filtering is useful for intelligent image processing, but it requires huge computational power. Pixel-parallel LSI implementation is one solution for real-time image processing. We have already proposed a new pixel-parallel Gabor filtering algorithm using transient states of resistive networks. This paper describes an LSI implementing this algorithm. This LSI has been designed using 0.35μm CMOS technology and based on the merged analog-digital circuit architecture using pulse-width modulation (PWM) signals. The LSI with a die size of 9.8 mm sq. includes 61 × 72-pixel processing units, and its maximum operation performance is 26 GOPS.
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Keyword(in English) Gabor filter / spatial filter / pixel-parallel processing / merged analog-digital circuit / PWM signal
Paper # SDM2004-126,ICD2004-68
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Conference Date 2004/8/12(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Pixel-Parallel Gabor Filtering LSI Based on Merged Analog/Digital Architecture
Sub Title (in English)
Keyword(1) Gabor filter
Keyword(2) spatial filter
Keyword(3) pixel-parallel processing
Keyword(4) merged analog-digital circuit
Keyword(5) PWM signal
1st Author's Name Takashi MORIE
1st Author's Affiliation Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology()
2nd Author's Name Jun UMEZAWA
2nd Author's Affiliation Graduate School of Advanced Sciences of Matter, Hiroshima University:(Present address)Now with Faculty of Engineering, Tokyo University of Agriculture and Technology
3rd Author's Name Atsushi IWATA
3rd Author's Affiliation Graduate School of Advanced Sciences of Matter, Hiroshima University
Date 2004/8/12
Paper # SDM2004-126,ICD2004-68
Volume (vol) vol.104
Number (no) 250
Page pp.pp.-
#Pages 5
Date of Issue