| Presentation | 2004/8/12 Access time and Chip area Evaluations of Bank based Multi-port Memory by Memory Generator Munetaka ASAO, Tomohiro INOUE, Tetsuo HIRONAKA, Tetsushi KOIDE, Hans JURGEN MATTAUSCH, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the comparison study of the realization technique of a bank type multi-port memory, in many cases chip area comparison is performed on limited range of parameter. This is because in order to measure chip area, we need many layouts based on a different parameter, and we need much time in order to design all the required layouts. Although there is also research of the area estimation based on equations, but including consideration of operation speed in it is difficult. So in this research the memory generator was created in order to enable the area estimation of the crossbar memory on the consideration of operation speed when the number of banks, the number of ports, data width, and address width differ. In the created memory generator, the automatic generation of the crossbar memory based on the HITACHI0.18μm CMOS process can be done. When the layout generated by the memory generator is compared with the manual designed layout with four ports, 32 banks, data width of I bit, and an address width of 15 bits, it turns out that an area increase was only 9%. Furthermore from the results, in proportion with the increase of data width and address width the estimated area increase decreases. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multiport-Memory / Memory Generator / Crossbar |
| Paper # | SDM2004-124,ICD2004-66 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/8/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Access time and Chip area Evaluations of Bank based Multi-port Memory by Memory Generator |
| Sub Title (in English) | |
| Keyword(1) | Multiport-Memory |
| Keyword(2) | Memory Generator |
| Keyword(3) | Crossbar |
| 1st Author's Name | Munetaka ASAO |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Tomohiro INOUE |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Tetsuo HIRONAKA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Tetsushi KOIDE |
| 4th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 5th Author's Name | Hans JURGEN MATTAUSCH |
| 5th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| Date | 2004/8/12 |
| Paper # | SDM2004-124,ICD2004-66 |
| Volume (vol) | vol.104 |
| Number (no) | 250 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |