Presentation | 2004/8/12 16MB/s High-Speed Multi-Level Programming Scheme for 4Gb AG-AND Flash Memory K. OTSUGA, H. KURATA, Y. SASAGO, T. ARIGANE, T. KAWAMURA, T. KOBAYASHI, Y. IKEADA, A. SATO, K. KOZAKAI, S. NODA, M. SIMIZU, O. TSUCHIYA, K. HURUSAWA, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper describes a high-speed multi-level programming scheme for 90-nm-node 4Gb flash memory which achieves programming throughput of 16MB/s. We developed two key technologies for high-speed multi-level programming. One is charge sharing scheme which reduces the dispersal of programming speed for every cell. The other is self boosting scheme which enables to supply drain voltage without pre-charging large capacitance of global-bit-line. The charge sharing scheme reduces verification time by 50%, and the self boosting scheme decreases pre-charging time by 82%. With these two schemes, we achieved programming throughput of 16MB/s for 4Gb AG-AND flash memory. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Flash Memory / AG-AND / Multi-Level Technology / Charge-Sharing Scheme / Self-Boosting Scheme |
Paper # | SDM2004-123,ICD2004-65 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2004/8/12(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | 16MB/s High-Speed Multi-Level Programming Scheme for 4Gb AG-AND Flash Memory |
Sub Title (in English) | |
Keyword(1) | Flash Memory |
Keyword(2) | AG-AND |
Keyword(3) | Multi-Level Technology |
Keyword(4) | Charge-Sharing Scheme |
Keyword(5) | Self-Boosting Scheme |
1st Author's Name | K. OTSUGA |
1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
2nd Author's Name | H. KURATA |
2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
3rd Author's Name | Y. SASAGO |
3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
4th Author's Name | T. ARIGANE |
4th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
5th Author's Name | T. KAWAMURA |
5th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
6th Author's Name | T. KOBAYASHI |
6th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
7th Author's Name | Y. IKEADA |
7th Author's Affiliation | Renesas Technology Corp., |
8th Author's Name | A. SATO |
8th Author's Affiliation | Renesas Technology Corp., |
9th Author's Name | K. KOZAKAI |
9th Author's Affiliation | Renesas Technology Corp., |
10th Author's Name | S. NODA |
10th Author's Affiliation | Renesas Technology Corp., |
11th Author's Name | M. SIMIZU |
11th Author's Affiliation | Renesas Technology Corp., |
12th Author's Name | O. TSUCHIYA |
12th Author's Affiliation | Renesas Technology Corp., |
13th Author's Name | K. HURUSAWA |
13th Author's Affiliation | Renesas Technology Corp., |
Date | 2004/8/12 |
Paper # | SDM2004-123,ICD2004-65 |
Volume (vol) | vol.104 |
Number (no) | 250 |
Page | pp.pp.- |
#Pages | 5 |
Date of Issue |