| Presentation | 2004/8/12 A Stacked Vertical MOS Four-Transistor SRAM Cell with 1/3 Size of a Conventional Memory Cell Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We developed a four-transistor SRAM cell with a stacked vertical poly-silicon PMOS for high-density SRAMs. This cell consists of two bulk NMOSs and the two vertical PMOSs stacked over the two NMOSs. Its size was only 1/3 of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | four-transistor SRAM cell / vertical MOS / electric-field-relaxation scheme / dual-word-voltage scheme |
| Paper # | SDM2004-121,ICD2004-63 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/8/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Stacked Vertical MOS Four-Transistor SRAM Cell with 1/3 Size of a Conventional Memory Cell |
| Sub Title (in English) | |
| Keyword(1) | four-transistor SRAM cell |
| Keyword(2) | vertical MOS |
| Keyword(3) | electric-field-relaxation scheme |
| Keyword(4) | dual-word-voltage scheme |
| 1st Author's Name | Akira Kotabe |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Kenichi Osada |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 3rd Author's Name | Naoki Kitai |
| 3rd Author's Affiliation | Hitachi ULSI Systems Co., Ltd. |
| 4th Author's Name | Mio Fujioka |
| 4th Author's Affiliation | Renesas Technology Copr. |
| 5th Author's Name | Shiro Kamohara |
| 5th Author's Affiliation | Renesas Technology Copr. |
| 6th Author's Name | Masahiro Moniwa |
| 6th Author's Affiliation | Renesas Technology Copr. |
| 7th Author's Name | Sadayuki Morita |
| 7th Author's Affiliation | Renesas Technology Copr. |
| 8th Author's Name | Yoshikazu Saitoh |
| 8th Author's Affiliation | Renesas Technology Copr. |
| Date | 2004/8/12 |
| Paper # | SDM2004-121,ICD2004-63 |
| Volume (vol) | vol.104 |
| Number (no) | 250 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |