Presentation 2004/7/7
A Study on a Front-end Chip for GPS Dual-band Receiver
MASAKI HARUOKA, YOSHIHIRO UTSUROGI, TOSHIMASA MATSUOKA, KENJI TANIGUCHI,
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Abstract(in English) A front-end chip for GPS dual-band receiver is integrated in a 0.25μm CMOS technology. The integrated receiver requires only a couple of external passive components for the input matching network and PLL loop filter. The receiver is an extension of the hartley architecture and shares RF block with L1/L2. Maximam conversion gain is 85dB, noise figure is 8dB and image-rejection ratio is 32dB. The receiver has a chip area of 3.16mm × 3.16mm, and consumes 35mA from a 2.5V supply.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Dual-band GPS Receiver / L1/L2 / LNA / Image-rejection mixer
Paper # ICD2004-58
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Conference Date 2004/7/7(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Study on a Front-end Chip for GPS Dual-band Receiver
Sub Title (in English)
Keyword(1) Dual-band GPS Receiver
Keyword(2) L1/L2
Keyword(3) LNA
Keyword(4) Image-rejection mixer
1st Author's Name MASAKI HARUOKA
1st Author's Affiliation Department of Electronics and Information Systems, Graduate School of Engineering, Osaka University:FURUNO ELECTRIC CO., LTD()
2nd Author's Name YOSHIHIRO UTSUROGI
2nd Author's Affiliation Department of Electronics and Information Systems, Graduate School of Engineering, Osaka University
3rd Author's Name TOSHIMASA MATSUOKA
3rd Author's Affiliation Department of Electronics and Information Systems, Graduate School of Engineering, Osaka University
4th Author's Name KENJI TANIGUCHI
4th Author's Affiliation Department of Electronics and Information Systems, Graduate School of Engineering, Osaka University
Date 2004/7/7
Paper # ICD2004-58
Volume (vol) vol.104
Number (no) 175
Page pp.pp.-
#Pages 6
Date of Issue