Presentation 2004/7/7
Under 0.5W 50Gb/s Full-Rate 4:1MUX and 1:4DEMUX in 0.13μm InP HEMT Technology
T. Suzuki, Y. Kawano, T. Takahashi, K. Makiyama, K. Sawada, Y. Nakasha, T. Hirose, M. Takikawa,
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Abstract(in English) -50-Gbit/s full-rate 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) ICs are developed using an InP HEMT technology. Design technologies, such as multi-phase clock architecture to maximize timing margin, and using InP HEMT technology allows a simultaneous pursuit of high performances and reducing power consumption more than 50 % compared with other device technologies. The MUX has the lowest rms jitter of 283 fs and peak-to-peak jitter of 1.78 ps in reported results. The DEMUX has a wide phase margin of 250° and a sensitivity of 80 mV at 40 Gbit/s. The power consumption was drastically reduced compared with that yet reported, the MUX and DEMUX achieved 450 mW and 490 mW from -1.5 V supply, respectively.
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Paper # ICD2004-50
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Conference Date 2004/7/7(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
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Title (in English) Under 0.5W 50Gb/s Full-Rate 4:1MUX and 1:4DEMUX in 0.13μm InP HEMT Technology
Sub Title (in English)
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1st Author's Name T. Suzuki
1st Author's Affiliation Fujitsu Laboratories Ltd.()
2nd Author's Name Y. Kawano
2nd Author's Affiliation Fujitsu Laboratories Ltd.
3rd Author's Name T. Takahashi
3rd Author's Affiliation Fujitsu Laboratories Ltd.
4th Author's Name K. Makiyama
4th Author's Affiliation Fujitsu Laboratories Ltd.
5th Author's Name K. Sawada
5th Author's Affiliation Fujitsu Laboratories Ltd.
6th Author's Name Y. Nakasha
6th Author's Affiliation Fujitsu Laboratories Ltd.
7th Author's Name T. Hirose
7th Author's Affiliation Fujitsu Laboratories Ltd.
8th Author's Name M. Takikawa
8th Author's Affiliation Fujitsu Laboratories Ltd.
Date 2004/7/7
Paper # ICD2004-50
Volume (vol) vol.104
Number (no) 175
Page pp.pp.-
#Pages 6
Date of Issue