Presentation | 2004/7/6 A multi-chip system mimicking an orientation selectivity of a primary visual cortical cell Kazuhiro SHIMONOMURA, Tetsuya YAGI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We describe a multi-chip aVLSI system which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation-selective chip which mimics the parallel and hierarchical architecture of visual system in the brain. The input image is filtered by the Laplacian-Gaussian-like receptive field of the silicon retina, and then it is transferred to the orientation-selective chip. The orientation-selective chip selectively aggregates multiple pixels, mimicking the feedforward model. The spatial properties of analog responses from the system were verified for different preferred orientation under indoor illumination. The multi-chip architecture used in this study is considered to be applicable in the implementation of higher order cells in the visual cortex. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | multi-chip / image processing / hierarchical processing / orientation selectivity |
Paper # | ICD2004-41 |
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Committee | ICD |
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Conference Date | 2004/7/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A multi-chip system mimicking an orientation selectivity of a primary visual cortical cell |
Sub Title (in English) | |
Keyword(1) | multi-chip |
Keyword(2) | image processing |
Keyword(3) | hierarchical processing |
Keyword(4) | orientation selectivity |
1st Author's Name | Kazuhiro SHIMONOMURA |
1st Author's Affiliation | Japan Science and Technology Agency:Department of Electronic Enginnering, Graduate School of Engineering, Osaka University() |
2nd Author's Name | Tetsuya YAGI |
2nd Author's Affiliation | Department of Electronic Enginnering, Graduate School of Engineering, Osaka University |
Date | 2004/7/6 |
Paper # | ICD2004-41 |
Volume (vol) | vol.104 |
Number (no) | 174 |
Page | pp.pp.- |
#Pages | 6 |
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