Presentation 2003/5/22
A 9μW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs
Koichiro Ishibashi, Takahiro Yamashita, Yukio Arima, Isamu Minematsu, Tetsuya Fujimoto,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have proposed Self-Adjusted Forward Body Bias (SAFBB) technique, in that the current flowing through pn junction in transistors is limited to make forward body bias maximum. A 32bit adder was fabricated using 0.13um CMOS technology. It consumes 9uW at 50MHz which corresponds 1/30 energy of conventional ones. We have also proposed a gated body technique. The forward bias is applied at operation mode to speed up circuits, and cut off at standby mode to decrease leakage currents. A estimated power of LSIs for mPEG2 encoder could be decreased to 1/5 of conventional method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Substrate bias / Body bias / Forward Bias
Paper # ICD2003-36
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Conference Date 2003/5/22(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 9μW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs
Sub Title (in English)
Keyword(1) Substrate bias
Keyword(2) Body bias
Keyword(3) Forward Bias
1st Author's Name Koichiro Ishibashi
1st Author's Affiliation Semiconductor Academic Research Center (STARC)()
2nd Author's Name Takahiro Yamashita
2nd Author's Affiliation Semiconductor Academic Research Center (STARC)
3rd Author's Name Yukio Arima
3rd Author's Affiliation Semiconductor Academic Research Center (STARC)
4th Author's Name Isamu Minematsu
4th Author's Affiliation Semiconductor Academic Research Center (STARC)
5th Author's Name Tetsuya Fujimoto
5th Author's Affiliation Semiconductor Academic Research Center (STARC)
Date 2003/5/22
Paper # ICD2003-36
Volume (vol) vol.103
Number (no) 89
Page pp.pp.-
#Pages 5
Date of Issue