| Presentation | 2003/5/22 An Autonomous Low-Power Architecture for a Chip Multi-Processor : Adaptive-Universal Control of Clock Frequency, Supply Voltage and Body Bias Masayuki MIYAZAKI, Goichi ONO, Hidetoshi TANAKA, Norio OHKUBO, Toshiyuki KAWAHARA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An autonomous adaptive-universal control of clock frequency, supply voltage, and body bias was developed as a low-power architectural solution. This technique optimizes performance-to-power ratio of a chip multi-processor (CMP) making each processor operate independently at the optimum condition. It consists of a compound built-in self-test (C-BIST) system and a self-instructed lool-up table (SI-LUT) system with the adaptive-universal control system. The C-BIST measures performance of each processor automatically while the CMP chip is being tested, and thus, it simplifies the chip design and shortens the chip-testing time. The SI-LUT provides the optimum clock frequency, Supply voltage, and body bias, which depend on the required performance. It uses the C-BIST data for its instruction, and it enables the autonomous control architecture. A 32-bit arithmetic-logic unit (ALU) is used to demonstrate the power optimization effect of the autonomous adaptive-universal control. The power consumption of the ALU is reduced by 1/10. In the CMP estimation, the proposed architecture reduces the power by 2/3, and shortens both the design and testing time by 1/10. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Autonomous Architecture / Universal control / Self instruction / Built-in self-test / Chip multi-processor |
| Paper # | ICD2003-34 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Autonomous Low-Power Architecture for a Chip Multi-Processor : Adaptive-Universal Control of Clock Frequency, Supply Voltage and Body Bias |
| Sub Title (in English) | |
| Keyword(1) | Autonomous Architecture |
| Keyword(2) | Universal control |
| Keyword(3) | Self instruction |
| Keyword(4) | Built-in self-test |
| Keyword(5) | Chip multi-processor |
| 1st Author's Name | Masayuki MIYAZAKI |
| 1st Author's Affiliation | Hitachi, Ltd., Central research Laboratory() |
| 2nd Author's Name | Goichi ONO |
| 2nd Author's Affiliation | Hitachi, Ltd., Central research Laboratory |
| 3rd Author's Name | Hidetoshi TANAKA |
| 3rd Author's Affiliation | Hitachi, Ltd., Central research Laboratory |
| 4th Author's Name | Norio OHKUBO |
| 4th Author's Affiliation | Hitachi, Ltd., Central research Laboratory |
| 5th Author's Name | Toshiyuki KAWAHARA |
| 5th Author's Affiliation | Hitachi, Ltd., Central research Laboratory |
| Date | 2003/5/22 |
| Paper # | ICD2003-34 |
| Volume (vol) | vol.103 |
| Number (no) | 89 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |