| Presentation | 2003/5/22 A Video Recognition Processor for Intelligent Cruise Control Based on 128 4-Way VLIW RISC Processing Elements Shorin KYO, Takuya KOGA, Shin'ichiro OKAZAKI, Ichiro KURODA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a 51.2GOPS video recognition processor, which achieves real-time multiple processing of in-vehicle video recognition applications in software, while at the same time it satisfies power efficiency requirements of an in-vehicle device. The chip integrates 128 4-way VLIW RISC micro-processors, each operating at 100 MHz, into a single chip. Hardware configurations of the chip are enhanced for supporting efficient execution of extended C language codes of algorithms based on four basic parallel methods. The results of a benchmark test using a weather robust lane-mark and vehicle detection application show that, the processor achieves a four times better performance while consumes less than one twentieth of the peak power consumption compared with an 2.4 GHz general purpose processor. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Parallel processor / VIdeo recognition LSI / ITS / Image processing / Parallel architecture / SIMD / VLIW |
| Paper # | ICD2003-29 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Video Recognition Processor for Intelligent Cruise Control Based on 128 4-Way VLIW RISC Processing Elements |
| Sub Title (in English) | |
| Keyword(1) | Parallel processor |
| Keyword(2) | VIdeo recognition LSI |
| Keyword(3) | ITS |
| Keyword(4) | Image processing |
| Keyword(5) | Parallel architecture |
| Keyword(6) | SIMD |
| Keyword(7) | VLIW |
| 1st Author's Name | Shorin KYO |
| 1st Author's Affiliation | Multimedia Research Laboratories, NEC Corporation() |
| 2nd Author's Name | Takuya KOGA |
| 2nd Author's Affiliation | Multimedia Research Laboratories, NEC Corporation |
| 3rd Author's Name | Shin'ichiro OKAZAKI |
| 3rd Author's Affiliation | Multimedia Research Laboratories, NEC Corporation |
| 4th Author's Name | Ichiro KURODA |
| 4th Author's Affiliation | Multimedia Research Laboratories, NEC Corporation |
| Date | 2003/5/22 |
| Paper # | ICD2003-29 |
| Volume (vol) | vol.103 |
| Number (no) | 89 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |