Presentation 2003/5/22
Variable-Kernel Flash-Convolution Image Filtering Processor
Kiyoto ITO, Makoto OGAWA, Tadashi SHIBATA,
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Abstract(in English) A VLSI image filtering processor featuring single-clock-cycle kernel convolution is presentd. A quaternary-tile pixel-mapping method has been developed in order to eliminate complicated memory address control and a large number of redundant memory accesses. As a result, a fast and low-power operation is achieved. In addition, any size of kernel can be utilized in image filtering, thus the processor is freely compatible to various advanced image-processing algorithms. The concept has been verified by a test chip fabricated in 0.18-μm 5-metal CMOS technology. Without pipelining, the processor operates at 50MHz with a 1.8V supply.
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Keyword(in English) Image Processing / Image Filtering / Logic-in-Memory
Paper # ICD2003-28
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Committee ICD
Conference Date 2003/5/22(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Variable-Kernel Flash-Convolution Image Filtering Processor
Sub Title (in English)
Keyword(1) Image Processing
Keyword(2) Image Filtering
Keyword(3) Logic-in-Memory
1st Author's Name Kiyoto ITO
1st Author's Affiliation Department of Frontier Informatics, School of Frontier Science, The University of Tokyo()
2nd Author's Name Makoto OGAWA
2nd Author's Affiliation Department of Frontier Informatics, School of Frontier Science, The University of Tokyo
3rd Author's Name Tadashi SHIBATA
3rd Author's Affiliation Department of Frontier Informatics, School of Frontier Science, The University of Tokyo
Date 2003/5/22
Paper # ICD2003-28
Volume (vol) vol.103
Number (no) 89
Page pp.pp.-
#Pages 6
Date of Issue