Presentation 2003/5/21
8Mbit Compiled SRAM Macro with Large Signal Sensing Scheme
Tetsuo ASHIZAWA, Wataru YOKOZEKI, Junichi MITANI, Michiari KAWANO,
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Abstract(in English) We developed an 8 Mbit SRAM macro with an access time of 2.76 ns that uses 0.11 μm CMOS technology. The large signal sensing scheme was used to increase access speed and stabilize operation. Since this scheme has a larger cell noise margin than conventional schemes, we were able to increase memory cell speed without increasing the cell area. A configuration of this macro can be changed by the compiler. We optimized the configuration for its capacity and the type of process to be used. In addition, we improved a conventional large signal sensing scheme. As a result, the improvement in speed was 33% over the conventional small signal sensing schemes.
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Keyword(in English) 0.11μm CMOS / SRAM / Large Signal Sensing Scheme / noise margin
Paper # ICD2003-25
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Conference Date 2003/5/21(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 8Mbit Compiled SRAM Macro with Large Signal Sensing Scheme
Sub Title (in English)
Keyword(1) 0.11μm CMOS
Keyword(2) SRAM
Keyword(3) Large Signal Sensing Scheme
Keyword(4) noise margin
1st Author's Name Tetsuo ASHIZAWA
1st Author's Affiliation Advanced CMOS Technology Dept., Fujitsu Ltd.()
2nd Author's Name Wataru YOKOZEKI
2nd Author's Affiliation FRAM Dept., Fujitsu Ltd.
3rd Author's Name Junichi MITANI
3rd Author's Affiliation Technology Development Div., Fujitsu Ltd.
4th Author's Name Michiari KAWANO
4th Author's Affiliation Technology Development Div., Fujitsu Ltd.
Date 2003/5/21
Paper # ICD2003-25
Volume (vol) vol.103
Number (no) 88
Page pp.pp.-
#Pages 4
Date of Issue