| Presentation | 2003/5/21 16.7fA/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors Kenichi OSADA, Yoshikazu SAITOH, Koichiro ISHIBASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Tunnel leakage currents become the dominant from of leakage as MOS technology advances. An electric-field-relaxation scheme that suppresses these currents is described. Cosmic-ray-induced multi-errors have now become a serious problem at sea level. An alternate error checking and correction architecture for the handling of such errors is also described, along with the application of both schemes in an ultra-low-power 16-Mbit SRAM. A test chip fabricated by usign 0.13-μm CMOS technology showed. per-cell standby-current values of 16.7fA at 25℃ and 101.7fA at 90℃. The chip provided a 99.5% reduction in soft errors under accelerated neutron-exposure testing.. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SRAM / low standby current / gate tunnel leakage / cosmic ray / ECC |
| Paper # | ICD2003-24 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/5/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 16.7fA/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | low standby current |
| Keyword(3) | gate tunnel leakage |
| Keyword(4) | cosmic ray |
| Keyword(5) | ECC |
| 1st Author's Name | Kenichi OSADA |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Yoshikazu SAITOH |
| 2nd Author's Affiliation | Semiconductor & Integrated Circuits, Hitachi, Ltd. |
| 3rd Author's Name | Koichiro ISHIBASHI |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| Date | 2003/5/21 |
| Paper # | ICD2003-24 |
| Volume (vol) | vol.103 |
| Number (no) | 88 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |