Presentation 2003/5/21
A 320-ps access, 3-GHz Cycle, 144-Kb SRAM Macro in 90-nm CMOS Technology
Hideo AKIYOSHI, Hiroshi SHIMIZU, Takashi MATSUMOTO, Katsuyoshi KOBAYASHI, Yasuhiro SANBONSUGI,
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Abstract(in English) A 320-ps access, 3-GHz cycle, 144-Kb SRAM macro was developed in 90-nm CMOS technology. This macro adopted an all-stage reset type control signal generator and hierarchical bit line. These techniques enabled both the cycle and access speeds to be 1.7 times compared to the corresponding speeds available with 130-nm generation technology.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) 90nm CMOS / SRAM Macro / all-stage reset type control signal generator / hierarchical bit line / 3GHz
Paper # ICD2003-23
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Committee ICD
Conference Date 2003/5/21(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 320-ps access, 3-GHz Cycle, 144-Kb SRAM Macro in 90-nm CMOS Technology
Sub Title (in English)
Keyword(1) 90nm CMOS
Keyword(2) SRAM Macro
Keyword(3) all-stage reset type control signal generator
Keyword(4) hierarchical bit line
Keyword(5) 3GHz
1st Author's Name Hideo AKIYOSHI
1st Author's Affiliation Fujitsu Limited()
2nd Author's Name Hiroshi SHIMIZU
2nd Author's Affiliation Fujitsu Limited
3rd Author's Name Takashi MATSUMOTO
3rd Author's Affiliation Fujitsu Laboratories Limited
4th Author's Name Katsuyoshi KOBAYASHI
4th Author's Affiliation Fujitsu Limited
5th Author's Name Yasuhiro SANBONSUGI
5th Author's Affiliation Fujitsu Limited
Date 2003/5/21
Paper # ICD2003-23
Volume (vol) vol.103
Number (no) 88
Page pp.pp.-
#Pages 6
Date of Issue