| Presentation | 2003/5/21 An Embedded Single-Chip Multiprocessor Masayuki SATO, Hiroyuki KONDO, Norio MASUI, Koichi ISHIMI, Satoshi KANEKO, Teruyuki ITOH, Naoto OKUMURA, Yukari TAKATA, Takashi HIGUCHI, Naoshi ISHIKAWA, Syunichi IWATA, Toru SHIMIZU, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 600MHz single-chip multiprocessor, which includes two M32R 32-bit CPU cores, 512-Kbyte shared SRAM and peripherals, is fabricated usign 0.15um CMOS process for embedded systems. This multiprocessor is based on symmetric multiprocessing (SMP), and supports modified -exclusive -shared -invalid (MEST) cache coherency protocol. The internal shared pipelined bus has low latency and large bandwidth (4.8-G byte/sec). The multiprocessor dissipates 800mW at 1.5V 600MHz multiprocessor mode. Standby power dissipation is less than 1.5mW at 1.5V. So the multiprocessor achieves higher performance and lower power consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | single-chip multiprocessor / SMP / embedded / Low power |
| Paper # | ICD2003-20 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/5/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Embedded Single-Chip Multiprocessor |
| Sub Title (in English) | |
| Keyword(1) | single-chip multiprocessor |
| Keyword(2) | SMP |
| Keyword(3) | embedded |
| Keyword(4) | Low power |
| 1st Author's Name | Masayuki SATO |
| 1st Author's Affiliation | System Core Technology Div., Renesas Technology Corp.() |
| 2nd Author's Name | Hiroyuki KONDO |
| 2nd Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 3rd Author's Name | Norio MASUI |
| 3rd Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 4th Author's Name | Koichi ISHIMI |
| 4th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 5th Author's Name | Satoshi KANEKO |
| 5th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 6th Author's Name | Teruyuki ITOH |
| 6th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 7th Author's Name | Naoto OKUMURA |
| 7th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 8th Author's Name | Yukari TAKATA |
| 8th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 9th Author's Name | Takashi HIGUCHI |
| 9th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 10th Author's Name | Naoshi ISHIKAWA |
| 10th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 11th Author's Name | Syunichi IWATA |
| 11th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| 12th Author's Name | Toru SHIMIZU |
| 12th Author's Affiliation | System Core Technology Div., Renesas Technology Corp. |
| Date | 2003/5/21 |
| Paper # | ICD2003-20 |
| Volume (vol) | vol.103 |
| Number (no) | 88 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |