| Presentation | 2003/5/21 A Debug System for Heterogeneous Multiple Processor in Single Chip Noriyuki MINEGISHI, Hirokazu SUZUKI, Ken-ichi ASANO, Keisuke OKADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can relaize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the VIdeo Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | VLSI / debug methodology / heterogeneous multiple processor / IEEE 1149.1 |
| Paper # | ICD2003-19 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/5/21(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Debug System for Heterogeneous Multiple Processor in Single Chip |
| Sub Title (in English) | |
| Keyword(1) | VLSI |
| Keyword(2) | debug methodology |
| Keyword(3) | heterogeneous multiple processor |
| Keyword(4) | IEEE 1149.1 |
| 1st Author's Name | Noriyuki MINEGISHI |
| 1st Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Hirokazu SUZUKI |
| 2nd Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 3rd Author's Name | Ken-ichi ASANO |
| 3rd Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 4th Author's Name | Keisuke OKADA |
| 4th Author's Affiliation | LSI Product Technology Unit, Renesas Technology Corporation |
| Date | 2003/5/21 |
| Paper # | ICD2003-19 |
| Volume (vol) | vol.103 |
| Number (no) | 88 |
| Page | pp.pp.- |
| #Pages | 6 |
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