Presentation 2003/5/21
A Single-Chip IEEE 802.11a MAC/PHY with a 32bit RISC Processor
Tatsuo Shiozawa, Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tetsuya Fujita, Unekawa Yasuo /, Takeshi Aikawa,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) An IEEE 802.11a compliant MAC/PHY processing chip has been successfully fabricated in 0.18um CMOS. 30M transistors are integrated on 10.91 x 10.91mm^2 die housed in a 361 pin PFBGA. The MAC functions are fully implemented by a firmware on an embedded 32-bit RISC processor and hardware acceleration logic. The PHY supports a complete set of data rates up to 54Mbps.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Wireless LAN / IEEE 802.11a / RISC / Power save / AGC / Equalizer / MAC / PHY
Paper # ICD2003-18
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Committee ICD
Conference Date 2003/5/21(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Single-Chip IEEE 802.11a MAC/PHY with a 32bit RISC Processor
Sub Title (in English)
Keyword(1) Wireless LAN
Keyword(2) IEEE 802.11a
Keyword(3) RISC
Keyword(4) Power save
Keyword(5) AGC
Keyword(6) Equalizer
Keyword(7) MAC
Keyword(8) PHY
1st Author's Name Tatsuo Shiozawa
1st Author's Affiliation TOSHIBA Corporation()
2nd Author's Name Toshio Fujisawa
2nd Author's Affiliation TOSHIBA Corporation
3rd Author's Name Jun Hasegawa
3rd Author's Affiliation TOSHIBA Corporation
4th Author's Name Koji Tsuchie
4th Author's Affiliation TOSHIBA Corporation
5th Author's Name Tetsuya Fujita
5th Author's Affiliation TOSHIBA Corporation
6th Author's Name Unekawa Yasuo /
6th Author's Affiliation TOSHIBA Corporation
7th Author's Name Takeshi Aikawa
7th Author's Affiliation TOSHIBA Corporation
Date 2003/5/21
Paper # ICD2003-18
Volume (vol) vol.103
Number (no) 88
Page pp.pp.-
#Pages 5
Date of Issue