Presentation 2003/5/21
1.27Gb/s/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme
Kouichi KANDA, Danardono Dwi ANTONO, Koichi ISHIDA, Hiroshi KAWAGUCHI, Tadahiro KURODA, Takayasu SAKURAI,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm^2. The interface utilizes capacitively coupled contactless minipads, return-to-V_
/2 signaling and sense amplifying flip-flops. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) I-O / high bandwidth / wireless connection / low power / high-density pad
Paper # ICD2003-16
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Committee ICD
Conference Date 2003/5/21(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 1.27Gb/s/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme
Sub Title (in English)
Keyword(1) I-O
Keyword(2) high bandwidth
Keyword(3) wireless connection
Keyword(4) low power
Keyword(5) high-density pad
1st Author's Name Kouichi KANDA
1st Author's Affiliation Institute of Industrial Science, University of Tokyo()
2nd Author's Name Danardono Dwi ANTONO
2nd Author's Affiliation Institute of Industrial Science, University of Tokyo
3rd Author's Name Koichi ISHIDA
3rd Author's Affiliation Institute of Industrial Science, University of Tokyo
4th Author's Name Hiroshi KAWAGUCHI
4th Author's Affiliation Institute of Industrial Science, University of Tokyo
5th Author's Name Tadahiro KURODA
5th Author's Affiliation Faculty of Science and Technology, Keio University
6th Author's Name Takayasu SAKURAI
6th Author's Affiliation Institute of Industrial Science, University of Tokyo
Date 2003/5/21
Paper # ICD2003-16
Volume (vol) vol.103
Number (no) 88
Page pp.pp.-
#Pages 4
Date of Issue