Presentation | 2003/5/21 10Gb/s./ch 50mW 120×130μm^2 Clock Recovery Circuit Shunichi KAERIYAMA, Masayuki MIZUNO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A clock and data recovery (CDR) circuit which obtains a clock signal from incoming NRZ serial bit sequence, is proposed for chip-to-chip communication. The proposed CDR circuit offers significantly reduced area and power requirements by using a gated-VCO-based architecture. This new architecture eliminates the need for a loop filter or multiple-phase-clock generators which occupy a large chip area. Tolerable jitter level is also improved by employing a newly developed phase-interpolator-based VCO-gating scheme. Fabricated in a 0.15μm standard CMOS technology, it successfully operates at 10Gb/s bandwidth/channel. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Clock Recovery / CDR / VCO |
Paper # | ICD2003-14 |
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Committee | ICD |
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Conference Date | 2003/5/21(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | 10Gb/s./ch 50mW 120×130μm^2 Clock Recovery Circuit |
Sub Title (in English) | |
Keyword(1) | Clock Recovery |
Keyword(2) | CDR |
Keyword(3) | VCO |
1st Author's Name | Shunichi KAERIYAMA |
1st Author's Affiliation | NEC Corporation() |
2nd Author's Name | Masayuki MIZUNO |
2nd Author's Affiliation | NEC Corporation |
Date | 2003/5/21 |
Paper # | ICD2003-14 |
Volume (vol) | vol.103 |
Number (no) | 88 |
Page | pp.pp.- |
#Pages | 6 |
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