Presentation 2004/1/30
Intra-Chip High-Speed Data Transfer Scheme Based on Autonomous Distributed Bus Control
Takashi TAKEUCHI, Akira MOCHIZUKI, Takahiro HANYU,
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Abstract(in English) This paper presents a new bus architecture for high-speed data transfer with vast quantities of data inside a VLSI chip. In the proposed bus architecture, since a bus is utilized as an "address bus" or a "data bus" in a time-sharing fashion, data can be transferred from one module to another with the maximum width of bus. Moreover autonomous distributed bus control in each module makes it possible to transfer data directly between modules, which results in high throughput of bus communication. It is demonstrated in case of a 64-line bus that the peak throughput of the proposed bus control is about four times higher than that of direct memory access control.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) interconnect capacitance / transfer speed / bit width / bus utilization / autonomous distributed / direct data transfer
Paper # CPM2003-182,ICD2003-221
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Conference Date 2004/1/30(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Intra-Chip High-Speed Data Transfer Scheme Based on Autonomous Distributed Bus Control
Sub Title (in English)
Keyword(1) interconnect capacitance
Keyword(2) transfer speed
Keyword(3) bit width
Keyword(4) bus utilization
Keyword(5) autonomous distributed
Keyword(6) direct data transfer
1st Author's Name Takashi TAKEUCHI
1st Author's Affiliation Research Institute of Electronic Communication, Tohoku University()
2nd Author's Name Akira MOCHIZUKI
2nd Author's Affiliation Research Institute of Electronic Communication, Tohoku University
3rd Author's Name Takahiro HANYU
3rd Author's Affiliation Research Institute of Electronic Communication, Tohoku University
Date 2004/1/30
Paper # CPM2003-182,ICD2003-221
Volume (vol) vol.103
Number (no) 648
Page pp.pp.-
#Pages 5
Date of Issue